Perhaps the most critical timing requirement for any memory element is its access time. As device size continues to shrink, access time is also decreasing, and an accurate measurement of access time is becoming increasingly complex.
One conventional method for measuring access time is to measure the access time from an input pad to an output pad using an external tester and subtract out any extra path delay. Such a test configuration is illustratively shown in FIG. 1. The external tester measures the time interval between application of the input signals at the input pads and the sensing of the output signal at the output pad. This time interval may be defined as follows:Ttotal=T(input pad)+T(input glue interface)+Taa+T(MUX)+T(output glue interface)+T(output pad).To extract the actual access time, the tester then switches the MUX to bypass the memory element and measures the time delay once again from the input pad to the output pad. This time interval is given by:Tdummy=T(input pad)+T(input glue interface)+T(MUX)+T(output glue interface)+T(output pad),where Taa=(Ttotal−Tdummy), and Taa is the required access time.
The above-described prior art method suffers from several drawbacks. First, measurement of the read access time for zero (Read 0) is not advisable for positive clock triggered memories, and vice-versa. That is, this system is not accurate for a Read 0 measurement since at the time of Ttotal calculation for Read 0, blocks from the input pad to the memory clock input are transferring clock rising edges, whereas blocks from the memory output to the output pad are transferring the 1 to 0 transition. This can be represented as:Ttotal=Tr(Input Pad)+Tr(Input Core logic)+Taa+Tf(Output Core logic)+Tf(Output Pad).When Tdummy is calculated the full system is transferring the positive edge of the clock, thus:Tdummy=Tr(Input pad)+Tr(Input Core Logic)+Tr(Output Core Logic)+Tr(Output pad); andTaa=Ttotal−Tdummy={Tr(Input Pad)+Tr(Input Core logic)+Taa+Tf(Output Core logic)+Tf(Output Pad)}−{Tr(Input pad)+Tr(Input Core Logic)+Tr(Output Core Logic)+Tr(Output pad}=Taa+{Tf(Output Core logic)+Tf(Output Pad)−Tr(Output Core Logic)+Tr(Output pad)},where Tr=rise time and Tf fall time. Accordingly, the error in the Read 0 measurement of a positive edge triggered memory is:ERROR={Tf(Output Core logic)+Tf(Output Pad)−Tr(Output Core Logic)+Tr(Output pad)}.
Another disadvantage of the above-described prior art approach is that the test pattern is established through the automatic test equipment (ATE). This increases the time of testing for embedded systems and hence increases the per chip cost of the product. Furthermore, IMS/HP/Teradyne, etc. testers are generally used for applying the test pattern in this system. These testers have input pattern delivery error of ±150 ps and output sampling of ±150 ps. This error gets added to the total error of the system, which is ˜±300 ps. Further still, the path mismatch between inputs A and B and the output of the multiplexer MUX introduces another potential source of inaccuracy.